AES Core

• Available on Tallika Secure SOC FPGA Platform with Tallika Security API
• Complies with FIPS 197 publication from NIST
• Support for 802.16 AE Specification
• Support for ITU G984-3 Specification
• Support for 128, 192, and 256 bit key lengths.
• ECB, CBC, OFB, CFB, CTR and CCM mode of operation.
• Supports Counter Mode
• Pipelined 64-bit Input/Output data path
• Supports loading and unloading data while data is being ciphered concurrently.
• Provides ability to pre-load Initialization Vector (IV)
• No dead cycles for key loading or mode switching providing an effective bandwidth of 2.9 Gbps
• Proven in FPGA and at 250 MHz in 0.13u technology in system level IPSEC Applications
• Available Optional AHB Interface
  

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