Configurable Multi-Channel AHB GPDMA Core

The General Purpose DMA (GPDMA) core supports configurable number of DMA channels on AHB bus, using 2 AHB masters. Each DMA channel enables movement of data from a source AHB address to destination AHB address, for a programmed count. Each channel executes a command stored in a descriptor. Several descriptors can be linked in a linked list before the DMA completes. (Product Brief)

Features:

• Available as fully integrated into Tallika's Secure SOC FPGA Platform
• Supports user configurable number of DMA channels.
• Uses 2 AHB masters, and 1 AHB slave.
• AHB 2.0 (32-bit) compliant.
• Supports SINGLE, INCR, INCR4 AHB transfers
• Linked List of descriptors having command and status enables multiple data movements to be done before completion interrupt.
• DMA request inputs for source and destination control DMA access time
• Programmable source and destination inputs for each DMA channel.
• 16 Byte register buffer per channel
• Fully synchronous design without latches.
• Silicon Proven
• Fully integrated with Tallika's Security API Library on Secure SOC Platform

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