IPSEC Packet Processing Core

Tallika’s Transmit/Receive IPSEC core is a silicon proven, flexible and scalable packet processing core - silicon proven and currently in production silicon.

Features:

• The IPSEC block supports Ethernet In (cleartext or ciphertext) and Ethernet Out (ciphertext or cleartext) —Fully Compliant with RFC 2401.
• IPv4 with IP option headers
• Automatic insertion/deletion of ESP/AH headers and trailers
• ESP Cipher algorithms supported are DES, 3DES, AES128, AES192, AES256 in CBC Mode, and AES128, AES192, AES256 in Counter Mode
• ESP and AH Authentication algorithms supported are HMAC-SHA1, HMAC-MD5, HMAC-SHA1-96, HMAC-MD5-96, AES-XCBC-MAC-96
• Anti-Replay Option Per Security Association (SA)
  IPSec Sequence Number overflow detection/event generation
• Transmit SA Lifetime time-timeout and byte-timeout checks.
• “Soft” (early warning of SA expiration, creating event) and “hard” (drop all further datagrams) timeout limits.
  Supports Ethernet frames of type DIX, IEEE 802.3 SNAP with optional VLAN
• Ethernet Jumbo frame support supports frame size upto 9200B
• Support for configurable number of Security Associations, each based on an SA index resulting from an external IPV4 classification
• Local storage/maintenance of statistics compatible with Microsoft’s Security API
• Aggregate 200 Mbps to 2.9 Gbps IPSEC throughput per channel at 250 MHz for AES-SHA1 as measured on the encrypted port
• 250 MHz Operation in 0.13u technology
  

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