Some Technical Papers from Tallika Team Members

• DDR Timing Closure: Physical Design and STA Methodology, Synopsys User Group Conf, Boston 2004.
• An RTL Designer’s Cookbook for RPP, Synopsys User Group Conf., 2003.
• Integration Of Large ASICs in a ‘Startup Mode', Synopsys User Group Conf. San Jose2002
• Security Chip Design Speeds on to Silicon, Integrated Systems Design magazine, March 1, 2002
• Physical Design Challenge of a Huge Security Processor, Aurora 2002.
• A Hierarchical Implementation Methodology for Large, Complex, Deep Sub-micron ASICs. Design Automation and Test Conf. Europe 2001
• RTL Low Power Techniques for System-On-Chip Designs, Synopsys User Group Conf. 1999.